The gates of a MOS transistor may be formed by depositing a layer of dielectric on a semiconductor substrate, and by covering this layer of dielectric with a stack of layers containing a metal layer. Etching steps are subsequently implemented for bounding the gates of the transistors within the multilayer thus formed.
The physical-chemical composition of the gate metal regions varies depending on the type of conduction and on the desired threshold voltage for the MOS transistor. In other words, a transistor of the N type and a transistor of type P comprise metal layers having different physical-chemical compositions.
Currently, the formation of these different metal gates comprises steps for deposition of different metal layers associated with steps for etching into these layers leading, for some of them, to opening up the layer of underlying dielectric.
However, etching away a metal layer with an endpoint on a portion of gate dielectric layer may damage this gate dielectric layer. A damaged gate dielectric layer may lead to electrical leakage between the gate region of a transistor and the underlying regions of this transistor.